The power-optimized switch for cloud ToR refresh and AI edge deployments. 40% more efficient than incumbent solutions.
Bandwidth
Power
Latency
SerDes
Process

Drive continuous innovation through fully programmable, software-defined switching. XISA gives you assembly-level access to programmable engines. No vendor lock-in.

Reduce infrastructure sprawl with efficient, workload-optimized switching. 40% lower power consumption than incumbent 12.8T switches. Sub-700ns latency.
Evolve your network to deliver more performance from your existing investments. UEC-ready for emerging AI networking standards.
128 × 100G PAM4 LR SerDes with industry-leading reach. No retimers required for in-rack DAC connections, reducing BOM cost and latency.
64K queues with fine-grained per-flow scheduling. Absorb worst-case microbursts while maintaining consistent tail latency.
Dynamic buffer allocation across all ports. No stranded memory; maximum utilization under variable traffic patterns.
<100 microsecond link recovery handled in microcode. Far faster than BGP convergence for rapid failover.
X2 is built on the X-Switch parallel execution architecture. Unlike traditional match-action pipelines, X-Switch executes instructions across programmable micro-engines simultaneously, maintaining line rate without recirculation penalties.
X2 integrates with industry-standard network operating systems and provides a complete development toolkit for custom implementations.
Full SONiC and SAI integration with production-ready drivers
Complete toolchain including compiler, simulator, debugger
Instruction-accurate emulation for pre-silicon development
P4-like compiler support with direct XISA mapping
Available with NDA access
Production-ready 1RU switch systems available directly. 12.8T configurations: 32×400G, 64×200G, 128×100G.