12.8 Tbps. Under 200 Watts. Fully programmable.

The power-optimized switch for cloud ToR refresh and AI edge deployments. 40% more efficient than incumbent solutions.

  • 12.8 Tbps

    Bandwidth

  • < 200 W

    Power

  • < 700 ns

    Latency

  • 128 × 100 G

    SerDes

  • 5 nm

    Process

Why X2

Open architecture icon
Open architecture

Drive continuous innovation through fully programmable, software-defined switching. XISA gives you assembly-level access to programmable engines. No vendor lock-in.

Operational efficiency icon
Operational efficiency

Reduce infrastructure sprawl with efficient, workload-optimized switching. 40% lower power consumption than incumbent 12.8T switches. Sub-700ns latency.

Future-proof investment icon
Future-proof investment

Evolve your network to deliver more performance from your existing investments. UEC-ready for emerging AI networking standards.

Trusted by

Powering the world's most demanding infrastructure.

Starlink

Xsight's X2 chip will form an integral part of the terabit routing needs of the next generation of Starlink satellites.

Michael Nicolls

VP Starlink Engineering, SpaceX

Oxide Logo

This represents switching silicon's x86 moment. What we believed was possible in switching is now available as product.

Bryan Cantrill

CTO, Oxide Computer Company

Key features

  • Arros transfer up down
    Native 100 G SerDes

    128 × 100G PAM4 LR SerDes with industry-leading reach. No retimers required for in-rack DAC connections, reducing BOM cost and latency.

  • Stack icon
    X-IQ Intelligent queuing

    64K queues with fine-grained per-flow scheduling. Absorb worst-case microbursts while maintaining consistent tail latency.

  • Database icon
    Fully shared packet buffer

    Dynamic buffer allocation across all ports. No stranded memory; maximum utilization under variable traffic patterns.

  • Restore icon
    Fast link recovery

    <100 microsecond link recovery handled in microcode. Far faster than BGP convergence for rapid failover.

X-Switch architecture

X2 is built on the X-Switch parallel execution architecture. Unlike traditional match-action pipelines, X-Switch executes instructions across programmable micro-engines simultaneously, maintaining line rate without recirculation penalties.

X2 Diagram mobile

Software and SDK

X2 integrates with industry-standard network operating systems and provides a complete development toolkit for custom implementations.

  • SONiC/SAI

    Full SONiC and SAI integration with production-ready drivers

  • X-SDK

    Complete toolchain including compiler, simulator, debugger

  • XBM

    Instruction-accurate emulation for pre-silicon development

  • XASM

    P4-like compiler support with direct XISA mapping

Specifications

Downloads

  • X2 Product brief

    2-page technical summary

    Download
  • Cloud ToR whitepaper

    Cloud‑optimized ToR switch

    Download
  • X-Switch ISA

    An Open Ethernet Switch ISA

    Download

Design-In Resources

Available with NDA access

  • Functional specifications
  • Reference schematics
  • HW design guidelines
  • SI/PI resources
  • SDK and X-HAL samples
  • System quick-start guides
Access Full Technical Library

Get started with X2

Production-ready 1RU switch systems available directly. 
12.8T configurations: 32×400G, 64×200G, 128×100G.

Silicon integration

For OEMs building custom platforms on X2 silicon.

Partner solutions

Deploy with turnkey systems from our ecosystem partners.