The world's first open switch ISA

XISAᵗᵐ (Xsight Instruction Set Architecture) is the programming specification for X-Switch silicon. Build custom network functions with full visibility into silicon behavior.

Read XISA white paper
Terminal coding screen

What is XISA

Just as x86 and Arm define how software interacts with CPUs, XISA defines how software interacts with Ethernet switch silicon. It's the first fully documented, openly available instruction set for programmable switching.

  • Like ARM for mobile

    Standard ISA enables ecosystem

  • Like x86 for servers

    Open architecture drives innovation

  • XISA for switches

    First open switch standard

Business benefits 
of openness

  • Eye icon

    Full transparency

    No "black box" architectures. Understand exactly how your switch processes packets.

  • Chart icon

    Build custom data planes

    Create P4 data planes optimized for your specific use cases.

  • Device desktop icon

    Extend without hardware

    Add new protocol support in software without waiting for new silicon.

  • Users icon

    Community innovation

    Benefit from ecosystem innovation and contribute back.

  • Lock icon

    Avoid lock-in

    Standard programming model across Xsight platforms.

  • Crystal ball icon

    Future-proof investment

    Your code and expertise transfer across silicon generations.

Architecture overview

XISA consists of two instruction sets: Parser ISA for packet parsing and header extraction, and MAP ISA for the programmable match-action pipeline. Both execute in parallel across dedicated micro-engines.

XISA diagram mobile

  • Parser ISA

    Walks header fields and generates lookup keys. Deterministic execution with protocol graph traversal.

  • MAP ISA

    Handles packet processing with parallel threads and async accelerators. Flexible instruction ordering and elastic resource allocation.

Key advantage

Traditional pipelines execute serially with fixed stage budgets. XISA executes in parallel across thousands of MAP cores, maintaining line rate up to the instruction budget for each packet size.

Download XISA White paper

Architecture comparison

Fixed pipeline
P4-mapped pipeline
XISA (Open ISA)
Programmability
Limited to pre-defined features
P4-level abstraction only
Full assembly-level access
Transparency
Black box
Compiler-dependent
Fully documented
Performance Impact
None (but inflexible)
Recirculation penalties
Line-rate maintained
Resources
Resources are isolated and explicitly bound to a specific pipeline stage
Resources are isolated and explicitly bound to a specific pipeline stage
Fully shared and elastic resources

What industry leaders say

Starlink logo

Xsight's X2 chip will form an integral part of the terabit routing needs of the next generation of Starlink satellites.””

Michael Nicolls

VP Starlink Engineering, SpaceX

Read more
Oxide logo

X2 represents what we see as the x86 moment for datacenter networking.””

Bryan Cantrill

CTO, Oxide Computer

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