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Xsight Labs has pioneered a "No Compromise" programmable architecture. Traditionally, programmable switches suffered from performance trade-offs (higher latency or lower bandwidth). Our X-Series Architecture delivers full programmability with ultra-low latency (<500ns) and line-rate performance even at minimum packet sizes (256B), all while maintaining industry-leading power efficiency.
XISA is our Open Instruction Set Architecture. We have posted it on GitHub to democratize Ethernet connectivity. By making the ISA open, we allow a robust software ecosystem and toolchain to grow organically, similar to the open-source success of Linux, ensuring customers aren't locked into proprietary, "black box" processing.
Our switches are designed for the lowest Total Cost of Ownership (TCO). For example, the X2-12.8T consumes less than 200W—roughly 40% less power than competing 12.8T switches. This leads to massive OpEx savings and allows for simplified system designs with smaller heat sinks and fewer fans.
The X2 is purpose-built for the AI era. It is optimized for interconnecting AI/ML, storage, and compute clusters. It supports the Ultra Ethernet Consortium (UEC) requirements and is designed to handle the massive, bursty data flows typical of modern AI workloads.
Yes. The X2 is future-proofed for the 800G optics ecosystem and is currently available in configurations like 16 x 800G (QSFP or OSFP).
X-IQ™ is our intelligent queuing and shared memory architecture. It dynamically optimizes packet processing to reduce "tail latency" and improve Flow Completion Times (FCT), ensuring that AI training jobs aren't stalled by a few slow packets.
X-View™ provides real-time telemetry for best-in-class network visibility. It allows operators to identify congestion, packet loss, or latency issues instantly, enabling proactive management of AI fabrics.
X-PND™ (Elastic Resource Allocation) allows for the flexible sharing of control tables. This means the switch can be reconfigured to adapt to different application needs, emerging protocols, or specific vendor features without hardware changes.
X2 utilizes a fully shared packet buffer architecture. Unlike sliced memory designs used by competitors, our shared memory ensures that high-intensity bursts (common in AI/Storage) are absorbed without dropping packets.
Xsight Labs provides the industry’s only integrated Internal Traffic Generator (ITG), allowing the switch to generate line-rate traffic internally without the need for expensive external test equipment. This enables operators to perform "pre-flight" network stress tests, validate link integrity, and benchmark performance immediately upon installation, significantly accelerating the deployment of large-scale AI clusters.
Yes. Our products feature full SAI (Switch Abstraction Interface) and SONiC integration, allowing for seamless deployment into existing open-source data center environments.
Absolutely. Because the data plane is fully programmable and supports a "booked-ended" approach with NICs/DPUs, users can implement proprietary congestion management and fine-grained flow control (X-FC™).
Yes. To accelerate time-to-market, we support a high-fidelity instruction-accurate simulator that allows developers to validate code and features without physical hardware. Furthermore, our solution integrates with GNS3, enabling users to model and simulate complex network topologies and large-scale AI fabrics in a virtual sandbox, ensuring seamless integration before site deployment.
The E-Series is specifically designed to provide the highest performance-per-watt in the industry. The E-Series focuses on delivering energy-efficient, for power-constrained environments like hyperscale edge and traditional cloud data centers.
By utilizing an architecture optimized for ultra-low power consumption, the E-Series significantly reduces the cooling and electricity requirements of a data center. This allows operators to increase port density within the same power envelope, delaying the need for costly facility upgrades.
Yes. Like the rest of the Xsight Labs portfolio, the E-Series supports SAI (Switch Abstraction Interface) and integrates seamlessly with SONiC, ensuring that it fits into modern, automated network management workflows without proprietary friction.
Unlike traditional DPUs that rely on rigid, fixed-function hardware pipelines (slow path/fast path), the E1 is built on a truly software-defined architecture. It places up to 64 Arm® N2 cores directly in the data path, allowing networking, storage, and security functions to be defined entirely in software. This ensures that the E1 can process 800 Gbps of traffic without the misalignments or performance hits typically seen when moving traffic between hardware accelerators and general-purpose cores.
Yes. The E1 can be an Edge Server. Available as a 1RU appliance, it features high-density compute, integrated 800G networking, and massive PCIe Gen5 expandability. This allows it to act as a single-box solution for edge applications such as CDN media controllers, AI inference gateways, or distributed firewalls replacing the need for separate x86 servers and dedicated NICs.
The E1 follows a standard Linux programming model. Because it is Arm SystemReady™ , it can run unmodified Linux distributions (e.g., Ubuntu, Debian) and standard cloud-native applications. Developers can use familiar tools like DPDK, SPDK, and XDP to build custom data planes, ensuring the fastest time-to-market without having to learn proprietary, vendor-specific languages.
The E1 is a key enabler for the Open Flash Platform (OFP), which flattens AI storage architecture. By using the E1 to manage storage logic directly, GPUs can access memory across the network at 800 Gbps without traversing legacy x86 storage servers. This serverless approach reduces energy consumption by up to 90% and slashes storage TCO by half.
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