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Xsight Labs has pioneered a "No Compromise" programmable architecture. Traditionally, programmable switches suffered from performance trade-offs (higher latency or lower bandwidth). Our X-Series Architecture delivers full programmability with ultra-low latency (<500ns) and line-rate performance even at minimum packet sizes (256B), all while maintaining industry-leading power efficiency.

XISA is our Open Instruction Set Architecture. We have posted it on GitHub to democratize Ethernet connectivity. By making the ISA open, we allow a robust software ecosystem and toolchain to grow organically, similar to the open-source success of Linux, ensuring customers aren't locked into proprietary, "black box" processing.

Our switches are designed for the lowest Total Cost of Ownership (TCO). For example, the X2-12.8T consumes less than 200W—roughly 40% less power than competing 12.8T switches. This leads to massive OpEx savings and allows for simplified system designs with smaller heat sinks and fewer fans.

The X2 is purpose-built for the AI era. It is optimized for interconnecting AI/ML, storage, and compute clusters. It supports the Ultra Ethernet Consortium (UEC) requirements and is designed to handle the massive, bursty data flows typical of modern AI workloads.

• Throughput: Up to 12.8 Tbps full-duplex.
• SerDes: 128 x 112G SerDes, allowing for retimer-less designs.
• Port Density: Supports up to 32 x 400G or 16 x 800G ports in a 1RU form factor.
• Latency: Ultra-low latency (<500ns).

Yes. The X2 is future-proofed for the 800G optics ecosystem and is currently available in configurations like 16 x 800G (QSFP or OSFP).

X-IQ™ is our intelligent queuing and shared memory architecture. It dynamically optimizes packet processing to reduce "tail latency" and improve Flow Completion Times (FCT), ensuring that AI training jobs aren't stalled by a few slow packets.

X-View™ provides real-time telemetry for best-in-class network visibility. It allows operators to identify congestion, packet loss, or latency issues instantly, enabling proactive management of AI fabrics.

X-PND™ (Elastic Resource Allocation) allows for the flexible sharing of control tables. This means the switch can be reconfigured to adapt to different application needs, emerging protocols, or specific vendor features without hardware changes.

X2 utilizes a fully shared packet buffer architecture. Unlike sliced memory designs used by competitors, our shared memory ensures that high-intensity bursts (common in AI/Storage) are absorbed without dropping packets.

Yes. Our products feature full SAI (Switch Abstraction Interface) and SONiC integration, allowing for seamless deployment into existing open-source data center environments.

Absolutely. Because the data plane is fully programmable and supports a "booked-ended" approach with NICs/DPUs, users can implement proprietary congestion management and fine-grained flow control (X-FC™).

The E-Series is specifically designed to provide the highest performance-per-watt in the industry. The E-Series focuses on delivering energy-efficient, high-radix switching for power-constrained environments like hyperscale edge and traditional cloud data centers.

By utilizing an architecture optimized for ultra-low power consumption, the E-Series significantly reduces the cooling and electricity requirements of a data center. This allows operators to increase port density within the same power envelope, delaying the need for costly facility upgrades.

Yes. Like the rest of the Xsight Labs portfolio, the E-Series supports SAI (Switch Abstraction Interface) and integrates seamlessly with SONiC, ensuring that it fits into modern, automated network management workflows without proprietary friction.