800 G. 75 W. 64 Arm N2 cores.
The industry’s first and only fully software-defined 800G DPU delivering double the performance at half the power.
800 Gbps
Throughput
75 W
Power
64 Arm cores
In data path
5 nm
Process
SBSA level 6
Arm SystemReady
Why E1
Software-defined architecture
Accelerate innovation and efficiency with easily programmable, software-defined silicon built for rapid development. Program with XDP, DPDK, SPDK. No proprietary SDK required. Arm System Ready.
On-path CPU fabric
The only DPU with no exception-handling slow path” with “The only DPU that doesn’t need a separate exception-handling slow path.
Built to scale
Converge compute, storage, and networking to simplify and scale your infrastructure.
Key features
64 Arm Neoverse N2 cores in the data path. 64 MB system cache with coherent interconnect eliminates slow-path bottlenecks.
800 Gbps networking with programmable parser.
PCIe Gen5 delivers 2Tbps bidirectional to the host.
Line-rate crypto at full wire speed with no throughput penalty.
DDR5 at 5.2GT/s across 4 channels with inline encryption.
Form factors
Choose your deployment model. All form factors share the same E1 silicon, software stack, and feature set.
E1-Server
1RU Edge Server
Complete 1RU system with integrated 800G networking.
- 19-inch chassis
- 2 × PCIe Gen5 expansion slots
- Available in full and half length
Software-defined switches and DPUs. Open standards. Industry-leading performance per watt.
E1-AIC
PCIe Add-in card
Drop 800G DPU into many PCIe Gen5 servers.
- FH3/4L form
- Multi-host with two PCIe Gen5 x16, Edge connector and MCIO
- Root-port mode
- 32/64 GB DDR5 on-board
Software-defined switches and DPUs. Open standards. Industry-leading performance per watt.
E1-SoC
System-on-Chip
Direct silicon access for custom system builds.
- Design-in support
- SDK and toolchain
Software-defined switches and DPUs. Open standards. Industry-leading performance per watt.
Technical specifications
| Processing | 64 Arm Neoverse N2 cores (ARMv9.0-A), 32MB L3 cache |
| Memory | 4× DDR5-5200 with inline AES-XTS encryption |
| Networking | 2× 400G Ethernet (800G total), 8× 112G PAM4 SerDes |
| PCIe | 40 Gen5 lanes (2 Tbps bidirectional), SR-IOV, Scalable IOV |
| Crypto | AES-GCM (IPsec), AES-XTS (storage), line-rate |
| Process | TSMC 5nm |
| Certifications | SBSA Level 6 |
| Power | 75 W |
Downloads
Design-In Resources
Available with NDA access
- Functional specifications
- Reference schematics
- HW design guidelines
- SI/PI resources
- SDK and X-HAL samples
- System quick-start guides
Get Started with E1
Program your DPU with the Linux tools you already know. Download the product brief or talk to our team about your deployment.
