200G. Up to 22 Arm N2 cores. Linux data plane.

The reach of a full DPU architecture at edge power budgets, one software stack from 200G to 800G, and no vendor lock-in at either end.

  • 200 Gbps

    Throughput

  • 12 MB

    Internal RAM (SLC or direct mapped)

  • 22 Arm N2 cores

    In data path

  • 16 PCIe Gen5 lanes

    Plus 4 management lanes

  • SDN data planes

    Linux distros

Why E1L

Ethernet SSD icon
Ethernet SSD with on-device compute

With an SSD controller and an NVMe-oF bridge that sits in front of the flash, E1L makes the most of on-device compute capabilities.

Unified storage pipe icon
One device across network, storage, and security

Featuring line-rate IPsec crypto, a unified storage pipe, and a 16-lane PCIe Gen5 fabric with SR-IOV — all integrated into one processor.

Lock icon
No vendor lock-in at either end

E1L uses open standards on the network side and a customizable PCIe fabric on the host side. Your architecture; your choice of hosts, drives, and operating systems.

3 configurations, one shared software stack.

Bring Software-Defined Infrastructure to Every Socket.

  • E1L-8

    • 8 cores
    • 8 MB SLC
    • 1× DDR5-5200
  • E1L-16

    • 16 cores
    • 8 MB SLC
    • 1× DDR5-5200
  • E1L-22

    • 22 cores
    • 12 MB SLC
    • 2× DDR5-5200

Form factors

Choose your deployment model. All form factors share the same E1L silicon, software stack, and feature set.

E1L-COM-Express COM Express Type 7 module

E1L-COM-EXPRESS

COM Express module

A standard COMe card, optimal for control-plane applications.

E1L-Server 1RU Edge Server

E1L-SERVER

1RU Edge Server

A 1RU compute system with 200G of integrated network, optimal for edge-compute workloads.

E1L-SoC Data Processing Unit silicon
E1L-SoC

Deployed as a DPU for distributed services, or as a host for scale-out. Same software, feature set, and interoperability across every variant.

Key features

  • Arm SystemReady. Unmodified Linux distros with XDP and DPDK/SPDK data planes.
  • Up to 200 Gbps of accelerated networking with a programmable parser.
  • Up to 22 Arm Neoverse N2 cores across three models.
  • Line-rate AES-GCM for IPsec ESP and UDP SEC.
  • 16 PCIe Gen5 lanes (plus 4 management lanes), 4 dual-mode controllers, and SR-IOV support up to 64K PF/VFs.

Technical specifications

Processing
8, 16, or 22 Arm Neoverse N2 cores, up to 12 MB system level cache
Memory
Up to 2× DDR5 at 5200 MT/s with memory encryption
Networking
1× 200G or 4× 100/50/25/10G over four 112G SerDes
PCIe
16 Gen5 lanes (plus 4 management lanes), 4 dual-mode controllers, SR-IOV up to 64K PF/VFs
Crypto
Line-rate AES-GCM (IPsec ESP, UDP SEC) · line-rate AES-XTS block storage crypto
Storage
T10-DIF/DIX, CRC GMAC, and scrub CRC protection offloads · stateless offloads: checksum, RSS, TSO, RoCEv2 iCRC
Certifications
Arm SystemReady for running unmodified Linux distros
Availability
Sampling from Q2 2027

Downloads

  • E1L Product brief

    3-page technical summary

    Download
  • E1L Product infographic

    One-page visual overview

    Download

Design-In Resources

Available with NDA access

  • Functional and Hardware specifications
  • DPDK sample applications
  • HW design guidelines
  • Reference designs
  • Performance benchmarks
Request NDA Access

Get started with E1L

Bring the full E-Series architecture to your edge power budget. E1L samples from Q2 2027 — talk to our team now about early access and design-in.