Filter, steer, and monitor traffic at 12.8 Tbps line rate on X2 silicon, with brokering logic you program instead of a feature set fixed at tape-out. 12.8 Tbps line rate • 1M+ table entries • 1RU under 475W
Just as x86 and Arm define how software interacts with CPUs, XISA defines how software interacts with Ethernet switch silicon. It's the first fully documented, openly available instruction set for programmable switching.

X2 removes the trade-off. It is a 12.8 Tbps programmable Ethernet switch built on the Xsight Instruction Set Architecture (X-ISA), the first fully open instruction set for Ethernet switch silicon. Brokering, filtering, and gateway logic run as software on the packet-forwarding engine at full line rate, in under 200W. When your visibility fabric needs a new capability, you write it, load it, and keep the same hardware.
X2 combines the throughput of a data center switch with the packet manipulation depth that visibility and gateway workloads demand. Four capabilities do the work.
The X-ISA parser walks up to 256 bytes of headers and generates lookup keys in software. Filter, classify, and steer at 12.8 Tbps with no recirculation penalties.
128 x 100G PAM4 SerDes support 25 to 800 GbE port speeds. More than 1M table entries hold filtering and forwarding rules, 8x the scale of incumbent 12.8T silicon.
In-band telemetry, sFlow, postcards, microburst detection, black hole localization, and any-cause verbose mirroring give the visibility fabric its own visibility.
X-PND allocates fully shared memory between control tables and packet buffer, so a filter-heavy broker profile and a buffer-heavy gateway profile run on the same chip.
Three deployment models cover visibility fabrics, gateway functions, and custom in-network processing. Each runs on X2-based open networking platforms shipping today.
Aggregate monitored traffic from production links, filter it in the X-ISA data plane, and distribute it to analysis tools at line rate.
Run cloud and carrier gateway services, including Carrier NAT and load balancing, on X2-based platforms instead of racks of x86 appliances.
Build brokering features the silicon vendor never shipped: proprietary header parsing, custom tunnel termination, in-band telemetry insertion, and packet tracing, all written against a published instruction set.
Three ways to build a brokering layer, in ascending order of programmability and service depth.
Fixed-function broker appliance
The incumbent approach. A fixed-pipeline switch ASIC or x86 appliance delivers today's filtering feature set. New encapsulations, telemetry formats, or steering behaviors wait for the vendor's next hardware generation, and x86 datapaths are limited to 100G and 200G connectivity.
X2 programmable broker
An X2-based open networking platform, such as the Edgecore Universal ToR or Interface Masters Tahoe 3832 EX, runs brokering logic in X-ISA software at 12.8 Tbps line rate. Filtering behavior changes by loading new code, not new hardware.
Enhanced switch appliance (X2 + E1)
The Interface Masters Tahoe 3828 EXA adds two E1 800G DPUs to the X2 switch, combining 11.2T of L2-L4 brokering with 1.6T of stateful L4-L7 processing in 1RU at under 475W. One platform covers packet brokering, gateway services, and advanced instrumentation telemetry.
X2 contributes the programmable data plane that brokering and gateway workloads run on: 12.8 Tbps of non-blocking switching, more than 1M table entries, and an open instruction set that puts filtering logic under your control. Full specifications, SKU variants, and the software stack live on the product page. X2 Programmable Ethernet Switch, GA since November 2024.

Industry-leading technology partnerships that enable silicon performance, interoperability, and ecosystem compatibility.
Universal ToR switch platform on X2 silicon, with Network Packet Broker named among its supported applications.
Tahoe 3828 EXA (X2 + E1) and Tahoe 3832 EX (X2) enhanced switch appliances, shipping to strategic customers from Q1 2026.
FabricFlow packet broker engine hosted on the Tahoe 3828 EXA.
What's next
Visibility and gateway layers are becoming software problems. As links move to 400G and 800G, the platforms that filter, steer, and inspect that traffic need line rate and feature velocity at the same time, and fixed-function silicon delivers only one of the two. Open, efficient, and programmable infrastructure closes that gap.
The Xsight Accelerate program packages what a brokering or gateway project needs to start: software assets, technical documentation, performance benchmarking, architectural blueprints, and starter development kits, backed by an ODM and software partner ecosystem already shipping X2-based platforms.
The Accelerate program provides software assets, technical documentation, performance benchmarking, architectural blueprints, and starter development kits for teams building on X2.