About Xsight Labs
Xsight Labs is building the open, programmable silicon that powers cloud and AI infrastructure. Our X-Series Ethernet switches deliver 12.8 Tbps at sub-700ns latency on an open ISA. Our E1 DPU runs 800 Gbps with 64 Arm cores in the data path. Both are in production today, with deployments at operators building modern infrastructure. We're a fabless team in Kiryat Gat, Boston, Raleigh-Durham, and the Bay Area.
Our teams are located and operate globally in Israel, the US, Europe, and Asia.
Description
Summary
We're hiring a senior circuit design engineer to design and optimize the analog and mixed-signal core of our custom SRAM — bitcells, sense amplifiers, write drivers, and periphery logic — on our most advanced process node. You'll work closely with the design lead and layout team to hit aggressive power, speed, and area targets while managing the tighter noise margins and higher variation inherent to leading-edge silicon.
Responsibilities
- Design and simulate bitcell arrays, sense amplifiers, write drivers, and decoders under advanced-node device models
- Run corner and Monte Carlo simulations to validate margin across voltage, temperature, and the wider process variation seen at advanced nodes
- Optimize circuits for target PPA specs in collaboration with the design lead, accounting for elevated leakage and reduced voltage headroom
- Work with layout engineers to resolve matching, parasitic, and floorplan issues that are more pronounced at advanced geometries
- Debug silicon bring-up issues and correlate simulation results to measured data, including divergence specific to new-node effects
- Document design decisions and maintain design specs through the project lifecycle
Requirements
Required qualifications
- 8+ years of analog/mixed-signal circuit design experience, with direct SRAM or embedded memory design on advanced process nodes
- Hands-on experience with FinFET or GAA/nanosheet device behavior, including short-channel effects and elevated variation
- Strong understanding of bitcell operation, sense amp topologies, and noise margin analysis under low-voltage, high-variation conditions
- Proficiency with SPICE-class simulators and standard analog design flows, including statistical/variation-aware simulation
- Comfortable working across multiple PVT corners and interpreting Monte Carlo results at advanced-node variation levels
Preferred qualifications
- Direct experience on a leading-edge node tapeout (within one or two generations of the foundry's most advanced offering)
- Experience with multi-port or dual-rail SRAM designs
- Familiarity with silicon debug and characterization at advanced nodes