About Xsight Labs
Xsight Labs is building the open, programmable silicon that powers cloud and AI infrastructure. Our X-Series Ethernet switches deliver 12.8 Tbps at sub-700ns latency on an open ISA. Our E1 DPU runs 800 Gbps with 64 Arm cores in the data path. Both are in production today, with deployments at operators building modern infrastructure. We're a fabless team in Kiryat Gat, Boston, Raleigh-Durham, and the Bay Area.
Description
Summary
We're hiring a senior circuit design engineer to design and optimize the analog and mixed-signal core of our custom SRAM — bitcells, sense amplifiers, write drivers, and periphery logic — on our most advanced process node. You'll work closely with the design lead and layout team to hit aggressive power, speed, and area targets while managing the tighter noise margins and higher variation inherent to leading-edge silicon.
Responsibilities
- Design and simulate bitcell arrays, sense amplifiers, write drivers, and decoders under advanced-node device models
- Run corner and Monte Carlo simulations to validate margin across voltage, temperature, and the wider process variation seen at advanced nodes
- Optimize circuits for target PPA specs in collaboration with the design lead, accounting for elevated leakage and reduced voltage headroom
- Work with layout engineers to resolve matching, parasitic, and floorplan issues that are more pronounced at advanced geometries
- Debug silicon bring-up issues and correlate simulation results to measured data, including divergence specific to new-node effects
- Document design decisions and maintain design specs through the project lifecycle