About Xsight Labs
Xsight Labs is building the open, programmable silicon that powers cloud and AI infrastructure. Our X-Series Ethernet switches deliver 12.8 Tbps at sub-700ns latency on an open ISA. Our E1 DPU runs 800 Gbps with 64 Arm cores in the data path. Both are in production today, with deployments at operators building modern infrastructure. We're a fabless team in Kiryat Gat, Boston, Raleigh-Durham, and the Bay Area.
Our teams are located and operate globally in Israel, the US, Europe, and Asia.
Description
Summary
We're looking for a senior layout design engineer with deep experience in custom memory layout at advanced process nodes to translate our SRAM circuit designs into manufacturable, matched, and parasitic-optimized silicon. Layout at the leading edge involves tighter design rules, multi-patterning and EUV constraints, and much less margin for error than at mature nodes.
Responsibilities
- Create custom layout for bitcell arrays, sense amp periphery, and decoder logic under advanced-node design rules
- Ensure tight matching and symmetry across critical circuit paths where advanced-node variation makes mismatch more costly
- Run and close DRC, LVS, and parasitic extraction under complex multi-patterning or EUV-based design rule decks
- Work with circuit designers to iterate on floorplan and minimize parasitic impact on timing/power, which is more sensitive at advanced geometries
- Collaborate directly with the foundry or PDK team on manufacturability, restrictive design rules, and process-specific constraints
- Support silicon debug by tracing layout-related root causes of failures, including those specific to advanced-node patterning
Requirements
Required qualifications
- 8+ years of custom IC layout experience, with specific SRAM or embedded memory layout on advanced process nodes
- Direct experience laying out designs under multi-patterning or EUV design rule constraints
- Strong command of DRC/LVS tools and custom layout editors at advanced nodes
- Deep understanding of matching techniques and parasitic-aware layout practices where margins are tight
- Experience closing layout on aggressive area targets without compromising yield, under restrictive advanced-node design rules
Preferred qualifications
- Experience across multiple advanced-node foundry processes (not just one vendor)
- Familiarity with memory compiler layout generation or parameterized layout scripting
- Exposure to advanced packaging or 3D memory stacking layouts