Operators have told us they want DPU capability within the power envelopes they already rely on. Until now, bringing DPU offload into a power-constrained site has meant one of two things: a proprietary software stack sized for one chip, or leaving offload out and keeping the networking, security and storage work on the host CPU. Either way the edge ran differently from the data center.
Today we announced the E1L, the newest member of the E-Series. It brings fully programmable DPU capability, at up to 200G, to as little as 25 watts TDP, with typical draw of 15 watts, in its eight-core, 100G configuration. It is built for edge, embedded and other power-constrained infrastructure, and it runs the same architecture and the same software as the 800G E1. An offload written for one runs on the other. Sampling begins in the second quarter of 2027.
What the E1L is
The E1L is the E1 architecture scaled to a smaller power and space budget. It is offered with 8, 16 or 22 Arm Neoverse N2 cores and a configurable TDP of 25 W, 30 W or 40 W, with typical draw of 15 W, 18 W and 25 W. The eight-core configuration handles 100G and the 22-core configuration up to 200 Gbps; every configuration has the same four SerDes lanes. It is built on TSMC’s N5 process, the same node as the E1, so it does the same work in a smaller package with less energy and less heat.
Like the E1, it puts the Arm cores directly in the data plane, and every packet passes through them. There is no fixed pipeline with a few cores off to the side for the slow path. Built on Arm Neoverse CSS N2 and designed for Arm SystemReady compatibility, the E1L runs off-the-shelf Linux distributions and the frameworks infrastructure teams already use: XDP in the kernel, DPDK and SPDK in user space, with the Xsight E-SDK to take an offload from development into production. It ships as a discrete device, a COM Express module, and a 1RU server with 200G of integrated networking, all on the same software and feature set.
Why 25 watts matters
Take a security appliance or a storage system built around a fixed power supply, or a rack at an edge site on a fixed feed with no specialized cooling. The site has a set number of watts, and the host CPU has been covering both the application and the infrastructure work. A DPU at data-center power did not fit. With the E1L, the network data plane, line-rate cryptography such as IPsec, and storage services run on the DPU within the site’s existing power budget. The host cores go back to the application, and the data plane becomes software the operator or the appliance vendor can change. In many E1 deployments the DPU is the host, and we expect that to be more common with the E1L: the application runs on the Arm cores alongside the infrastructure services, and the separate host CPU goes away.
The same applies to smaller slots inside the data center. The COM Express version puts 8 to 22 Arm cores, DDR5 and PCIe Gen5 into a control-plane slot that has held far less compute, on the same Linux data plane as the rest of the E-Series.
One software stack from 100G to 800G
The part of the announcement that matters most to a team running the E1 today is that nothing changes in the software. An operator that runs the E1 in the data center can run the same transport, the same security policy and the same telemetry on the E1L, written once and qualified once. When the transport or the policy changes, the update is a software release to hardware already in the field, from the 25-watt device at a remote site to the 800G device in the core.
That is the protocol agility case extended to the edge. In February we showed a software-defined RoCEv2 running at 800G on the E1’s cores, and last month we described protocol agility: the ability to tune, extend or replace a transport in software, on hardware that is already installed. Alongside the E1, which draws under 75 W at 800G, the E-Series now runs one software stack from 100G at the edge to 800G in the core. For the companies that build on Xsight, that is one product line from a 25-watt device to a 1RU server, on standard Linux tools and with no proprietary licensing. The TCO methodology we published for the E1 applies to the E1L in the same way, with the power line adjusted for the smaller part.
E1L key specifications
- Compute: 8, 16 or 22 Arm Neoverse N2 cores
- Networking: up to 200 Gbps; four SerDes lanes in every configuration
- Memory: up to 2 DDR5-5200 interfaces with inline encryption
- Security: line-rate AES-GCM for IPsec and PSP offload, with separate AES-XTS engines for storage and AES-GCM engines for look-aside offloads
- Host interface: 20 PCIe Gen5 lanes across 6 dual-mode controllers with SR-IOV support
- Power: configurable 25 W, 30 W and 40 W TDP (typical draw 15 W, 18 W and 25 W)
- Software: off-the-shelf Linux distributions; XDP, DPDK and SPDK integration; the Xsight E-SDK for development through production
Availability
The E1L is scheduled to begin sampling in the second quarter of 2027. We will present it at the 2026 OCP Global Summit, October 12 to 15, in San Jose. E1L product details are on the E1L product page.