XISA glossary

Accelerator (coprocessor)

A hardware block that performs a common packet-processing task — hashing, checksum, metering, and counting — without consuming instruction slots. In XISA, accelerators are shared across MAP cores, and many run asynchronously while the program continues.

Assembly-level access

Programming the switch by writing instructions that the silicon executes directly, rather than describing intent in a higher-level language and relying on a compiler to map it onto fixed hardware stages.

Cross-connect

A forwarding behavior that maps traffic from one port or interface directly to another, without a full lookup. Used for pass-through paths, test configurations, and simple bridging.

Cursor (parser cursor)

A pointer the parser maintains into the incoming packet buffer. Instructions operate relative to the cursor position, and accelerators can advance it past headers the program does not need to inspect.

DASH

Disaggregated APIs for SONiC Hosts. A SONiC sub-project defining standard interfaces for offloading stateful network services — such as connection tracking and policy enforcement — to hardware.

Data path

The part of a network device that processes packets as they pass through, as distinct from the control plane that decides policy. A programmable data path means this processing can be changed in software.

Dependency checker

A mechanism that tracks registers awaiting a pending write-back and stalls any instruction that tries to read one before the result is ready, allowing instructions to be issued without waiting for earlier results.

Dynamic load balancing (DLB)

Distributing traffic across equal-cost paths using live conditions such as path occupancy rather than a fixed hash of header fields. Relevant to AI fabrics, where few large flows make static hashing uneven.

ECMP

Equal-Cost Multi-Path. Spreading traffic across several equally good routes, conventionally by hashing header fields so that every packet in a flow follows the same path, preserving ordering at the cost of even distribution.

Fixed-function pipeline

A switch architecture whose packet-processing stages are defined in silicon at design time. Behavior can be configured within the designed feature set, but new processing cannot be added after manufacture.

In-network computation

Performing calculations on data as it traverses the network rather than at an endpoint — for example aggregating values from many senders inside the switch, reducing the volume that reaches the receiver.

Instruction budget

The number of instructions available to process one packet at line rate for a given packet size. Smaller packets arrive more often, so the budget per packet is tighter.

Instruction set architecture (ISA)

The specification defining the instructions a processor executes, their encodings, and their effects. It is the contract between software and hardware; x86 and Arm are the best-known examples.

Line rate

Processing packets as fast as the interface can deliver them, with no loss and no backlog. Meaningful only when stated alongside the packet size and the program being run.

Longest-prefix match (LPM)

A lookup that selects the most specific matching entry — the one with the longest matching prefix. The standard method for IP routing table lookups.

MAP (Match-Action Processor)

The XISA engine that performs packet processing after parsing: classification, forwarding, security, and header editing. MAP cores process packets independently in run-to-completion mode, sharing instruction memory, scratchpad memory, and accelerators across the complex.

MAP ISA

The XISA instruction set for the Match-Action Processor, covering arithmetic and logic, memory access, table lookup, accelerator invocation, checksum handling, and packet transmission. Distinct from the Parser ISA, which serves a different engine.

Match-action

The processing model in which a packet is matched against table entries and a corresponding action is applied. The dominant abstraction in programmable switching, used by both P4 and XISA.

Metadata (standard metadata, SMD)

Information about a packet that travels alongside it through processing rather than existing in the packet itself — ingress port, parsing results, and error flags. In XISA the parser prepares standard metadata for the MAP.

Meter

A hardware function that measures traffic rate against a configured profile and marks or drops packets that exceed it. Also called a “policer”. Implemented as an accelerator so it does not consume instruction slots.

P4

An open, domain-specific language for describing packet processing in a target-independent way. Widely supported across programmable switching and constrained by the fixed-stage pipeline abstraction it assumes, which limits what can be expressed.

P4 compatibility

The ability to run programs written in P4 on a given target. On XISA, P4 is one route to the silicon; assembly-level programming is the other, for cases P4 cannot express.

Parser

The engine that reads a packet’s headers, works out which protocols are present, and extracts the fields for later processing needs. In XISA the parser is programmable and has its own instruction set.

Parser ISA

The XISA instruction set for the programmable parser, specialized for walking a protocol graph, extracting header fields, and passing user-defined metadata to a MAP core.

PFE (Programmable Forwarding Engine)

The XISA processing block comprising the programmable parser and the MAP complex, together with their shared instruction memory, scratchpad memory, and coprocessor accelerators. The unit within which a packet header is parsed and processed.

Programmable data path

A data path whose packet-processing behavior is defined in software after manufacture, allowing new protocols and new forwarding logic to be added without new silicon.

Protocol graph

The set of possible header sequences a parser may encounter, expressed as states and transitions. The parser walks this graph to establish a packet’s structure.

Recirculation

Sending a packet back through the processing pipeline for a second pass when one pass cannot complete the work. It consumes bandwidth, adds latency, and is a common cost of fixed-stage architectures.

Reparse

Returning a packet header to the parser for a further parsing pass, typically after the MAP has modified or decapsulated it. In XISA the reparse begins at a designated entry point with a supplied cursor offset.

RoCEv2

RDMA over Converged Ethernet version 2. A protocol for remote direct memory access across routable Ethernet networks, widely used in AI and HPC clusters and sensitive to loss and congestion.

Run-to-completion

A model in which one processing element handles a packet from start to finish, rather than passing it between fixed stages. Removes per-stage resource binding and allows flexible instruction ordering.

SAI

Switch Abstraction Interface. A standard API defining how network operating systems control switch silicon, allowing the same software to run across implementations from different vendors.

SONiC

Software for Open Networking in the Cloud. An open-source network operating system, originating at Microsoft, that runs on switch hardware from many vendors via SAI.

Ternary match

A lookup where entries may treat some bits as “don’t care,” allowing a single entry to match a range of values. Used for access control lists and classification.

UEC

Ultra Ethernet Consortium. An industry body defining Ethernet-based transport for AI and HPC workloads, addressing congestion control, multipathing, and loss recovery at cluster scale where conventional Ethernet transport behaves poorly.

XISA

Xsight Instruction Set Architecture. The published instruction set specification for X-Switch silicon, comprising the Parser ISA and the MAP ISA. Released under the Mozilla Public License version 2.