About Xsight Labs
Xsight Labs is building the open, programmable silicon that powers cloud and AI infrastructure. Our X-Series Ethernet switches deliver 12.8 Tbps at sub-700ns latency on an open ISA. Our E1 DPU runs 800 Gbps with 64 Arm cores in the data path. Both are in production today, with deployments at operators building modern infrastructure. We're a fabless team in Kiryat Gat, Boston, Raleigh-Durham, and the Bay Area.
Our teams are located and operate globally in Israel, the US, Europe, and Asia.
Description
Position Summary:
We are seeking an experienced and detail-oriented Physical Design Engineer to join our Advanced ASIC/SoC Development Team. In this role, you will be responsible for the complete RTL-to-GDSII physical implementation of high-performance, complex digital integrated circuits (ICs) built on advanced technology nodes (e.g., 7nm, 5nm, or below). You will collaborate closely with RTL design, architecture, DFT, and CAD team members to deliver power, performance, and area (PPA) optimized silicon on aggressive timelines.
Responsibilities:
- Design Implementation: Execute physical Design from RTL to GDS on advance technology of 5nm and below
- Timing and Power Integrity Closure: Perform Static Timing Analysis, Ensure Power Integrity and meet IR drop criteria.
- Physical Verification: Close DRC, LVS, ERC, ANT
- Work with global Engineer team to deliver design, ensuring design quality
Requirements
- Education: BS, MS in Electrical Engineering, electronics Engineering.
- Minimum of 3 years of hands-on experience in physical design engineering for complex integrated circuits.
- Proficiency in Synopsys (ICC2, Fusion Compiler, PrimeTime) or Cadence (Innovus, Genus)
- Scripting Languages: Strong skills in Tcl, Python, and Perl.
- Experience with advanced processes.