About Xsight Labs
Xsight Labs is building the open, programmable silicon that powers cloud and AI infrastructure. Our X-Series Ethernet switches deliver 12.8 Tbps at sub-700ns latency on an open ISA. Our E1 DPU runs 800 Gbps with 64 Arm cores in the data path. Both are in production today, with deployments at operators building modern infrastructure. We're a fabless team in Kiryat Gat, Boston, Raleigh-Durham, and the Bay Area.
Our teams are located and operate globally in Israel, the US, Europe, and Asia.
Description
The Team & Role Overview
This vacancy is situated within our core VLSI Organization. This unique hybrid role bridges embedded software development and pre-silicon design verification (DV). You will be responsible for bringing hardware components to life by developing specialized software kernels while rigorously verifying complex subsystem behaviors and system integration.
Operational Focus & Organizational Scope: Our team focuses squarely on pre-silicon execution and serves as a central technical anchor supporting hardware-software verification activities across the entire organization. In this role, you will act as a pivotal technical conduit connecting VLSI digital design, architecture, and system software to ensure robust subsystem execution and validation prior to tape-out.
High Impact on the DPU Product Line
You will have direct, hands-on impact on our DPU product line—our ultra-high-throughput silicon solution powering next-generation workloads. The Driver development and pre-silicon verification suites will directly dictate the stability, maximum bandwidth, and power efficiency of our advanced DPU subsystems, safeguarding first-pass silicon success.
Key Responsibilities
- Embedded SW Driver Development: Design, implement, and maintain specialized SW Drivers directly interacting with underlying hardware components, controllers, and digital logic.
- Pre-Silicon Design Verification (DV): Develop comprehensive verification environments, execute pre-silicon DV flows, author targeted test plans, and verify seamless HW/SW integration across complex subsystems.
- Cross-Organizational Technical Anchor: Serve as a core technical anchor supporting verification activities, flows, and inquiries across architecture, VLSI digital design, and software teams.
- HW/SW Boundary Debugging: Drive root-cause analysis for complex integration issues spanning firmware, subsystem controllers, and digital logic in simulation and emulation.
- Methodology & Flow Enhancement: Continuously optimize verification productivity, leveraging modern automation and AI-driven development practices to accelerate verification cycles.
Requirements
Education & Experience Requirements
- Academic Degree: B.Sc. in Electrical Engineering (EE) or Computer Engineering (CE) from a recognized academic institution.
- Experience: 2 to 3 years of hands-on professional industry experience in embedded software, firmware, or hardware design verification.
- Dedication & Leadership: Demonstrated track record of commitment and leadership through significant military service, volunteering, or meaningful community service.
Mindset & Working Style
- Proactive & 'Rosh Gadol' Mentality: Self-motivated engineer with high accountability who assumes end-to-end ownership, anticipates edge cases, and drives solutions across functional boundaries.
- Analytical & Debug Acumen: Strong first-principles problem-solving approach with genuine passion for hardware-software co-design, debugging, and pre-silicon exploration.
Core Technical Skills
- Programming & OOP: Strong programming foundation in C and C++ with rigorous Object-Oriented Programming (OOP) methodology.
- Verification Know-How: Solid grasp of Design Verification (DV) concepts, testbench architecture, and hardware/firmware integration.
- Debugging Experience: Proven hands-on experience conducting root-cause debugging at the intersection of hardware logic and software drivers.
Preferred Qualifications & Advantages (Nice-to-Have)
- DDR & Memory Subsystems: Familiarity with or knowledge of DDR memory protocols (DDR4, DDR5, LPDDR, or HBM) and memory controller subsystems – Significant Advantage.
- DV Flow Execution: Experience executing DV flows using SystemVerilog, UVM, Specman (e-language), or coverage-driven verification.
- Cache Coherency: Solid understanding of cache coherency protocols, interconnects, and multi-core memory hierarchies.
- Embedded Microcontrollers: Experience developing firmware or verifying subsystems based on ARM Cortex-M7 or equivalent cores.
- AI-Driven Development: Familiarity with and proactive adoption of modern AI-driven development and verification assistance tools.