Software Security Architect

We are looking for an experienced Software Security Architect to join Xsight Labs' Software

organization and lead the security architecture for our current and next-generation SoCs and DPU

products.

In this role, you will define the end-to-end security architecture and requirements spanning hardware,

firmware, boot software, operating systems, device management, and manufacturing/provisioning

flows. You will work closely with the HW Architecture team to define security capabilities for future

silicon generations, and with Firmware and Software teams at a hands-on level to drive these

capabilities from architecture through implementation and validation.

The position requires a combination of deep security-domain expertise, strong embedded/software

architecture skills, and the ability to translate customer and industry security requirements into

practical HW/SW designs.

Responsibilities

 Own the system and software security architecture for Xsight's SoCs and DPU products.

 Define security requirements and architecture for:

o Hardware and Silicon Root of Trust (RoT)

o Secure Boot and Trusted Boot chains

o Firmware authentication and code signing

o Measured Boot and device/firmware attestation

o Secure firmware update

o Key provisioning, key hierarchy, key rotation and revocation

o Anti-rollback protection and monotonic counters

o Device identity and certificate management

o Secure key storage, OTP/eFuse usage and lifecycle management

o Debug authentication and secure device lifecycle states

o Trusted Execution Environments and Arm TrustZone

o TPM 2.0 integration and PCR-based measurements

o Remote attestation using SPDM

o Isolation between trusted and non-trusted software components

 Define and document threat models, trust boundaries, attack surfaces and security requirements for new products.

 Translate customer, industry, and standards requirements into concrete HW, FW and SW architecture specifications.

 Write detailed security architecture, requirements, interface and design documents.

 Work closely with the HW Architecture and RTL teams during the definition of nextgeneration

devices, ensuring that the required primitives for Root of Trust, secure storage,

isolation, cryptography and attestation are designed into the silicon.

 Work hands-on with Firmware and Software developers to drive architecture into working

implementations, including design and code reviews, debugging and integration.

 Own selection and integration strategy for relevant industry standards and technologies such

as Caliptra, SPDM, DICE, TPM 2.0 and Arm TrustZone.

 Evaluate HW versus SW partitioning of security functionality and define interfaces between the

RoT/security subsystem and the rest of the SoC.

 Work with product, customer-facing and engineering teams to analyze customer security

requirements and identify architecture gaps.

 Participate in security reviews and help drive validation of security requirements from pre-silicon through bring-up and production.

Required Skills and Experience

 B.Sc. or M.Sc. in Computer Science, Computer Engineering, Electrical Engineering, or equivalent practical experience.

 10+ years of software, firmware or security engineering experience, with significant

experience architecting security for embedded systems, SoCs, servers, networking devices or similar products.

 Deep understanding of Root of Trust, Secure Boot, measured boot, chain of trust and

attestation architectures.

 Strong knowledge of cryptographic fundamentals:

o RSA / RSA-PSS

o ECC / ECDSA

o AES-GCM / AES-XTS

o SHA-2 / SHA-3

o Key derivation and key hierarchy

o Certificate and PKI concepts

o Random-number generation / entropy

 Experience designing firmware signing, authentication, update, rollback-prevention and

key-revocation mechanisms.

 Strong knowledge of TPM 2.0, PCRs and measured-boot flows.

 Experience with Arm security architecture, especially TrustZone, privilege/isolation

mechanisms and trusted firmware.

 Familiarity with SPDM and remote device attestation.

 Strong embedded development background using C/C++.

 Experience with low-level firmware, bootloaders, Linux and hardware/software interfaces.

 Ability to read hardware specifications and collaborate directly with ASIC architects and RTL engineers.

 Strong technical writing ability, including architecture specifications, requirements and detailed

design documents.

 Strong debugging and root-cause-analysis skills across HW/FW/SW boundaries.

Desired Knowledge and Experience

 Caliptra architecture, firmware and integration.

 DICE / Device Identifier Composition Engine, CDI and device identity.

 Arm Trusted Firmware / TF-A, Trusted Board Boot Requirements and X.509-based authenticated boot.

 SPDM 1.2/1.3, including measurements, challenge/authentication, certificates and remote attestation.

 MCTP transports and interaction with BMC/management architectures.

 PCIe TDISP / IDE and confidential-computing/device-isolation concepts.

 Secure manufacturing and provisioning, including HSM-backed signing/provisioning infrastructure.

 OTP/eFuse architecture, lifecycle states and ownership transfer.

 Secure and authenticated debug, including JTAG/debug authorization.

 Secure enclaves and hardware-backed Trusted Execution Environments.

 Hardware countermeasures against side-channel and fault-injection attacks.

 Secure RNG / TRNG and NIST SP 800-90 concepts.

 Hardware key vaults / isolated key storage and hardware crypto engines.

 Memory encryption and secure/replay-protected storage such as RPMB.

 Familiarity with FIPS 140-3, NIST security standards and security certification processes.

 Knowledge of Post-Quantum Cryptography and crypto-agility, particularly ML-DSA / SLHDSA

and hybrid signing approaches

Desired Knowledge and Experience

 Caliptra architecture, firmware and integration.

 DICE / Device Identifier Composition Engine, CDI and device identity.

 Arm Trusted Firmware / TF-A, Trusted Board Boot Requirements and X.509-based authenticated boot.

 SPDM 1.2/1.3, including measurements, challenge/authentication, certificates and remote attestation.

 MCTP transports and interaction with BMC/management architectures.

 PCIe TDISP / IDE and confidential-computing/device-isolation concepts.

 Secure manufacturing and provisioning, including HSM-backed signing/provisioning infrastructure.

 OTP/eFuse architecture, lifecycle states and ownership transfer.

 Secure and authenticated debug, including JTAG/debug authorization.

 Secure enclaves and hardware-backed Trusted Execution Environments.

 Hardware countermeasures against side-channel and fault-injection attacks.

 Secure RNG / TRNG and NIST SP 800-90 concepts.

 Hardware key vaults / isolated key storage and hardware crypto engines.

 Memory encryption and secure/replay-protected storage such as RPMB.

 Familiarity with FIPS 140-3, NIST security standards and security certification processes.

 Knowledge of Post-Quantum Cryptography and crypto-agility, particularly ML-DSA / SLHDSA and hybrid signing approaches.